About Me

Personal Background

After a 20+ year career in engineering, ranging from semiconductor process and circuit design to PC peripheral hardware development and finally enterprise IT engineering and architecture, I moved into technology writing and journalism. Since late 2005 I've been a regular writer on the IT trade press beat, primarily for Processor Magazine (www.processor.com/editorial). I am equally at home covering technical esoterica and big-picture business strategy and am well versed on the latest technology and IT industry trends. 

I've made many great industry contacts over the last few years, but am always looking for more, as well as interesting scoops or writing opportunities.


IT Services Engineer: Hewlett-Packard; Boise, ID
November 2001 – December 2005 (4 years 2 months)

IT service development and engineering in HP's (pre- and post-Compaq merger) primarily in managed hosting and Web/middleware services.

Information Technology Enginner:  Hewlett-Packard; Boise, ID
November 1991 – November 2000 (9 years 1 month)

IT infrastructure architecture and engineering and server-related, but also some network and security engineering.

Development Engineer: Hewlett-Packard
October 1988 – October 1991 (3 years 1 month)

R&D Engineer in the Boise Printer Division (Laserjet)

Integrated Circuit Designer: AT&T Bell Labs; Allentown, PA
July 1985 – September 1988 (3 years 3 months)

R&D Semiconductor Device Engineer: Micron Technology; Boise, ID
September 1984 – June 1985 (10 months)

Device physist developing new semiconductor processes/recipes via experimentation and computer modeling.

R&D Semiconductor Device Engineer: Mostek Corp.; Carrollton, TX
August 1983 – September 1984 (1 year 2 months)

Device physist on new semiconductor processes.


Stanford University: MS Electrical Engineering
1982 – 1983
Advisors were Jim Plummer and Robert Dutton.

Stanford University: BS Electrical Engineering
1980 – 1982

Boise State University: Math; pre-engineering major in university honors program
1978 – 1980